Many microprocessors use a hardware accelerator to perform coding for video encoding and decoding. The hardware accelerator, however, is fixed to a particular coding and decoding (codec) standard and cannot be used for new codec standards and certain abstractions from the codec, e.g., variations provided by a Network Abstraction Layer (NAL) that are used to provide variable bandwidth and network customization options under the International Telecommunication Union Telecommunications standardization sector (ITU-T) H.264 advanced video codec (AVC) standard. The AVC standard is defined, in part, in Motion Pictures Expert Group version 4 (MPEG-4), part 10. As a result, some coding tasks for network abstraction can not be performed in hardware, and in many instances can be performed in software.
In general, codecs implemented using an Application Specific Integrated Circuit (ASIC) are faster and more energy efficient than codecs implemented in software and executed on a central processing unit (CPU). For example, many chip manufacturers provide H.264 AVC hardware decoding units as part of a graphics processing unit (GPU). To facilitate hardware decoding, several public application programming interfaces (APIs) have been provided by hardware manufacturers and software Operating System (OS) providers, e.g., DirectX Video Acceleration (DXVA) is provided by Microsoft Corporation while Video Decode Acceleration Framework (VDA) is supplied by Apple, Inc. For royalty-free mobile platforms, OMX™ Integration Layer (IL) is provided by the Khronos Group. The above mentioned APIs can be used by setting decoder parameters or by sending NAL data to the hardware decoding unit. The hardware decoding unit preprocesses the video bit stream along with API calls. However, in many circumstances the hardware decoding unit will fail during NAL processing thereby resulting in a poor user experience.